The present invention relates to a method and a configuration for compensating for parasitic current losses in a memory cell array including word lines, bit lines which cross the word lines, and memory cells that are provided at points of intersection between the word lines and the bit lines and through which parasitic currents resulting in the parasitic current losses flow.
A memory cell array of a conventional MRAM is illustrated in FIG. 2 and described in greater detail below. In such a memory cell array, memory cells are located at points of intersection having total current levels which stipulate magnetic fields that are available locally for programming the memory cells and can fluctuate greatly. Since the memory cells have a magnetic hysteresis, and particular threshold values need to be exceeded in order to program them, such fluctuations in the magnetic field are extremely undesirable. Therefore, memory cells all having substantially the same structure and threshold values cannot be programmed by using the same magnetic fields.
It is accordingly an object of the invention to provide a method and a configuration for compensating for parasitic current losses in a memory cell array, which overcome the hereinafore-mentioned disadvantages of the heretofore-known methods and configurations of this general type and which permit magnetic fields of the same size to be provided for the individual memory cells in each case.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for compensating for parasitic current losses in a memory cell array. The method comprises providing the memory cell array with word lines, bit lines crossing the word lines at points of intersection, and memory cells disposed at the points of intersection for conducting parasitic current flows resulting in the parasitic current losses. Currents individually fed into the word lines and bit lines are proportioned, in such a way that a sum of currents flowing through the word lines and the bit lines associated with each individual point of intersection is substantially constant at the points of intersection.
In the method according to the invention, the word lines and bit lines are thus supplied with currents having a size which is proportioned by taking into account the voltage drop arising across each memory cell. This is done in such a way that the total current level at the points of intersection between the word lines and the bit lines has a value which is substantially constant over the memory cell array. In this context, it is naturally not necessary for exactly the same total current level to be present at all points of intersection. Instead, it is sufficient if the current level at the individual points of intersection has substantially the same size. This can also be achieved by virtue of particular groups of word lines and bit lines being driven by using the same current in each case, which means that certain tolerable discrepancies from the ideal total current level may arise within the individual group. However, in any case, the invention permits fundamental compensation of the parasitic current loss in the individual word lines and bit lines by merely ensuring that the currents supplied to these word lines and bit lines have sizes substantially compensating for the parasitic current losses.
With the objects of the invention in view, there is also provided a configuration for compensating for parasitic current losses in a memory cell array having word lines, bit lines crossing the word lines at points of intersection, and memory cells disposed at the points of intersection for conducting parasitic current flows resulting in the parasitic current losses. The configuration comprises word line drivers and bit line drivers for individually supplying differently proportioned currents to the word lines and the bit lines, causing a sum of currents flowing through the word lines and the bit lines associated with each individual point of intersection to be substantially constant at the points of intersection.
In accordance with a concomitant feature of the invention, the memory cell array is a memory cell array of an MRAM.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and a configuration for compensating for parasitic current losses, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.